1. Field of the Invention
The present invention relates to a memory system and a data writing method utilizing the memory system, and more particularly, to measures against a bit line failure of a nonvolatile semiconductor memory.
2. Description of the Related Art
In a nonvolatile semiconductor memory such as a NAND type flash memory, cell failure may occur before or after shipment of the memory. Such nonvolatile semiconductor memory, which may include cell failure, may be still utilized as storage devices by way of control of a controller. The controller controls the nonvolatile semiconductor memory on block-by-block basis, the block serving as an erasure unit when data is rewritten in the nonvolatile semiconductor memory. Refer to, for example, Jpn. Pat. Appln. KOKAI Publication No. 7-29392. However, with the trend of large scale integration and miniaturization of the nonvolatile flash memory, there have been substantiated not only the above-described failure controllable in block-by-block basis but also another failure called a “column failure”. The column failure gives undesirable influence on a plurality of blocks sharing the same bit line. Thus, it is impossible to manage such a column failure by way of block-by-block basis.
In the case where a memory cell array is managed on a block-by-block basis, when a write failure or an erasure failure is detected in a block serving as a write object or erasure object, a reserved block is used in place of the faulty block. However, when a column failure occurs, there may exist a write failure or an erasure failure in not only a block but also its reserved block, since these blocks generally share a bit line. When such a column failure occurs before shipment of a nonvolatile semiconductor memory product, it is possible to take measures by using a technique called column redundancy to program a decoder circuit so as to replace the faulty column with a redundancy column. Refer to, for example, Jpn. Pat. Appln. KOKAI Publication No. 2002-117692. However, when the column failure occurs after shipment of the nonvolatile semiconductor memory, it is impossible to carry out measures by using the column redundancy technique. In addition, in a system including the nonvolatile semiconductor memory and controller, even when a write error or an erasure error is detected in the nonvolatile semiconductor memory by the controller, the controller cannot detect whether or not such error is caused by the column failure.